1. Field of the Invention
The present invention relates to multi-gigabit transceivers (MGTs) located on a programmable logic device (PLD), such as a field programmable gate array (FPGA). More specifically, the present invention relates to a method and apparatus for providing variable-width data paths for use in the operation of an MGT on a PLD.
2. Related Art
In the past, multi-gigabit transceivers (MGTs) have not been included on programmable logic devices (PLDs) for various reasons. However, commonly owned, copending U.S. Patent Application entitled xe2x80x9cHigh Speed Configurable Transceiver Architecturexe2x80x9d filed concurrently, describes the manner in which MGTs can be included on a PLD, such as a field programmable gate array (FPGA). It would therefore be desirable to optimize the data paths between the core logic of a PLD and the MGTs located on the PLD.
PLD commonly includes one or more data paths, or collections of digital signals routed through the system during processing. The size of a collection, called the xe2x80x9cdata widthxe2x80x9d or xe2x80x9cdata path widthxe2x80x9d herein, depends on a number of factors. One factor in determining the data path width is the significance of the signals (i.e., the information that the signals represent, and the format of the signals). Another factor is the required speed of operation of the design. Yet another factor is the size constraints introduced by the design. Other factors may also possibly affect the data path width.
In some cases, it may be desirable to modify the width of a data path at some point in the design, changing the extent to which data is propagated in parallel. This may be necessary, for example, because of: different operating speeds in different portions of the design, or different constraints on the data width in different portions of the design. It may also be beneficial for this data width modification to be programmable.
One way of modifying the data path width is to completely modify the design of a system. However, this is a costly manner of modifying the data path width.
PLDS, such as FPGAs, are typically able to implement variable-width data paths by configuring and reconfiguring the PLD. However, such an implementation constitutes an inefficient use of programmable resources that preferably would be reserved for more significant design functions.
It would therefore be desirable to have a PLD capable of implementing a variable-width data path between the core logic of the PLD and the MGTs on the PLD, without requiring use of the programmable resources of the PLD core.
Accordingly, the present invention provides a transmit variable-width interface that can be programmed to convert an electronic digital data path that is either 1N, 2N, 4N, or 8N bits wide into a data path that is 2N bits wide, either by serializing bits (4N- or 8N-bit cases), re-clocking bits (2N-bit case), or grouping bits (1N-bit case). Conversely, a separate receive variable-width interface can be programmed to convert a data path 2N bits wide into a data path that is 1N, 2N, 4N, or 8N bits wide. The widths of the two variable-width data paths may be controlled independently.
The transmit and receive variable-width interfaces are coupled between an MGT and core logic of a PLD. In one embodiment, the MGT has a fixed internal data width of 2N bits, and the core logic of the PLD exhibits a selectable data width of 1N, 2N, 4N or 8N bits. The transmit variable-width interface operates to transfer variable-width data values from the core logic to the fixed-width data path of the MGT. Conversely, the receive variable-width interface operates to transfer fixed-width data values from the MGT to the variable-width path of the core logic.
The incoming and outgoing data paths of each of the variable-width interfaces have separate clocks signals that are synchronized such that small amounts of skew in these clock signals do not disrupt the operation of the variable-width interfaces. More specifically, these clock signals are synchronized such that falling edges of one clock signal correspond with rising edges of the other clock signal.
The present invention will be more fully understood in view of the following description and drawings.